Phase-locked loop (PLL) integrated circuits are frequently used to generate highly accurate internal clock signals on an integrated circuit substrate. As illustrated by FIG. 1, a conventional PLL integrated circuit 10 may include a phase detector 12, a charge pump 14, a loop filter 16, a voltage controlled oscillator (VCO) 18, a clock decoder and buffer 20, and a frequency divider 22. The phase detector 12 may be configured to generate UP and DOWN control signals in response to a reference clock signal (CKREF) and a feedback clock signal (CKVCO). In particular, the phase detector 12 may be configured to compare the phases of the clock signals and generate an active UP signal or an active DOWN signal when the feedback clock signal CKVCO lags or leads the reference clock signal CKREF. As will be understood by those skilled in the art, the reference clock signal (CKREF) may be a buffered version of an external clock signal (not shown) that is received by an integrated circuit chip. The charge pump 14 may be operative to convert the digitally encoded UP and DOWN control signals into an analog output (POUT) that sources current to or sinks current from the loop filter 16. The loop filter 16 is illustrated as generating a control voltage (Vcontrol), which is provided as an input to the VCO 18. The VCO 18 may generate a plurality of outputs, which are provided to the clock decoder and buffer 20. One of the outputs of the clock decoder and buffer 20 (shown as clock signal φ1) may be provided as an input to the frequency divider 22, which generates the feedback clock signal CKVCO. An active UP signal operates to increase the value of Vcontrol, which speeds up the VCO 18 and causes the feedback clock signal CKVCO to catch up with the reference clock signal CKREF. On the other hand, an active DOWN signal slows down the VCO 18 and eliminates the phase lead of the feedback clock signal CKVCO. These and other aspects of the PLL 10 of FIG. 1 are more fully illustrated and described at section 9.5.2 of a textbook by Jan M. Rabaey, entitled Digital Integrated Circuits: A Design Perspective, Prentice-Hall, ISBN 0-13-178609-1, pp. 540-542.
FIG. 2 illustrates a conventional charge pump 14 having both pull-up and pull-down sections. The pull-up section includes an NMOS pull-down transistor N1 in series with a resistor R1. A pull-up current mirror is provided by PMOS transistors P1 and P2. The NMOS pull-down transistor N1 is responsive to the UP control signal. When the UP control signal is active at a logic 1 level, the NMOS pull-down transistor N1 turns on and pulls-down the drain and gate of PMOS transistor P1. The feedback signal line NMOS_ON is also switched high-to-low. This causes both PMOS transistors P1 and P2 to turn on and provide a sourcing current (Isource) to the output terminal (POUT) of the charge pump 14. The pull-down section includes a PMOS pull-up transistor P3 in series with a resistor R2. A pull-down current mirror is provided by NMOS transistors N2 and N3. The gate of the PMOS pull-up transistor P3 is connected to an output of an inverter I1, which receives the DOWN control signal. When the DOWN control signal is active at a logic 1 level, the PMOS pull-up transistor P3 turns on and pulls-up the drain and gate of NMOS transistor N2. The feedback signal line PMOS_ON is also switched low-to-high. This causes both NMOS transistors N2 and N3 to turn on and withdraw a sinking current (Isink) from the output terminal POUT. When the control signals UP and DOWN are both active at logic 1 levels, the pull-up and pull-down sections are simultaneously active. The pull-up and pull-down sections of the charge pump may be balanced so that Isource equals Isink and no net current is provided to or withdrawn from the output terminal POUT. A similar charge pump is illustrated at FIG. 4 of commonly assigned U.S. Pat. No. 6,430,244 to Rhu, entitled “Digital Phase-Locked Loop Apparatus With Enhanced Phase Error Compensating Circuit,” the disclosure of which is hereby incorporated by reference.
FIG. 3A illustrates a conventional phase detector 12 that utilizes a delay device D1 to provide a dead zone compensation time interval during which both the UP and DOWN control signals are temporarily active. Maintaining the UP and DOWN control signals at active levels during an overlapping time interval prevents a “dead zone” from occurring when the phases of the reference clock signal CKREF and the feedback clock signal CKVCO are so closely aligned that the generation of any active UP control signal would otherwise be immediately canceled by the generation of any active DOWN control signal and vice versa. As described in U.S. Pat. No. 4,322,643 to Prescar and U.S. Pat. No. 6,192,094 to Herrmann et al., and in an article by X. Zhang entitled “Analysis and Verification on Side Effect of Anti-Backlash Delay in Phase-Frequency Detector,” Microwave Theory and Techniques Society (MTT-S) Digest, IEEE International Microwave Symposium, pp. 17-20, Jun. 8-13, 2003, the delay device D1 may also be referred to as an “anti-backlash” delay unit. The phase detector 12 is illustrated as including a pair of D-type flip-flops (DFF1 and DFF2), a NAND gate ND1, an inverter I2 and a delay device D1. The D-type flip-flops are synchronized with the reference and feedback clock signals CKREF and CKVCO. A rising edge of the reference clock signal CKREF will cause the true output Q1 of DFF1 to switch high and a rising edge of the feedback clock signal CKVCO will cause the true output Q2 of DFF2 to switch high. To prevent dead zone operation, the UP and DOWN control signals remain active whenever a rising edge of the reference clock signal CKREF is registered (by DFF1) while the DOWN control signal is active or whenever a rising edge of the feedback clock signal CKVCO is registered (by DFF2) while the UP control signal is active. Setting the UP and DOWN control signals to logic 1 levels causes the output of the NAND gate ND1 to switch high-to-low and the output of the inverter I2 to switch low-to-high. This low-to-high switching at the output of inverter I2 is delayed by a fixed time amount equal to T1, by the delay device D1. The delay T1 may be about 5 nanoseconds in some cases. The reset signal RST at the output of the delay device D1 will switch low-to-high some time after the output of the inverter I2 switches low-to-high in response to simultaneously active UP and DOWN control signals. When active, the reset signal RST operates to reset the flip-flops DFF1 and DFF2 (Q1=Q2=0). Upon reset, the UP and DOWN control signals will switch to inactive levels and the output POUT of the charge pump 14 of FIG. 2 will be disposed in a high impedance state. Operation of the phase detector 12 of FIG. 3A will now be described more fully with respect to FIGS. 3B-3C.
In FIG. 3B, a first rising edge of the reference clock signal CKREF causes the UP control signal at the true output Q1 of DFF1 to switch low-to-high. Following this, a first rising edge of the feedback clock signal CKVCO causes the DOWN control signal at the true output Q2 of DFF2 to switch low-to-high. This initial overlap of the active UP and DOWN control signals causes the input of the delay device D1 to switch high. Then, the reset signal RST switches low-to-high after a time period equal to about T1 (or equal to T1 if the delays associated with the logic elements ND1 and 12 are ignored). This time period T1 represents the duration of the dead zone compensation time interval during which both of the control signals UP and DOWN remain at active levels to prevent dead zone operation when the phases of the CKREF and CKVCO are closely aligned. In response to the low-to-high transition of the reset signal RST, the true outputs Q1 and Q2 are switched high-to-low and the output of inverter I2 then switches high-to-low. The high-to-low transition at the output of the inverter I2 is reflected in a high-to-low transition of the reset signal RST after a time period equal to T1. Unfortunately, the overlap between the active UP and DOWN control signals (i.e., true outputs Q1 and Q2) for a duration of about T1 causes the phase detector 12 of FIG. 3A to miss a rising edge of an incoming reference clock signal CKREF during the overlap time period. This missed edge is highlighted in FIG. 3B. As will be understood by those skilled in the art, this failure to recognize a rising edge of the incoming reference clock signal CKREF can cause gain inversion and reduce the lock time of the phase detector 12. Gain inversion takes place when the phase detector 12 outputs the wrong control signals and causes the phase differences between the reference clock signal CKREF and feedback clock signal CKVCO to increase rather than decrease. This is reflected in FIG. 3B by the failure to maintain an active UP control signal during the time period extending between the first and second rising edges of the feedback clock signal CKVCO. Accordingly, when the second rising edge of the feedback clock signal CKVCO is received, the DOWN control signal becomes active (thereby causing gain inversion) while the UP control signal remains inactive (when it should have been active in response to the missed clock signal update).
This gain inversion problem may also occur outside the dead zone compensation time interval. In particular, FIG. 3C illustrates how a clock signal update may be missed during the period when the reset signal RST is high and the true outputs Q1 and Q2 are held low. Thus, as illustrated by FIG. 3C, a time interval having a duration of about 2T1 represents a period during which clock signal updates are not possible within the phase detector of FIG. 3A.